Exemplary embodiments of the present invention relate to semiconductor device fabrication technology, and more particularly, to a semiconductor device having a resistive memory and a method for fabricating the same.
Extensive research is being conducted on next-generation memory devices that can replace dynamic random access memory (DRAM) devices and flash memory devices. Examples of the next-generation memory devices include resistive memory (ReRAM) devices. The resistive memory devices provide good characteristics at low fabrication costs. In particular, the resistive memory devices are esteemed as high-capacity memory devices because they have a very simple stacked structure of metal-insulator-metal.
A stacked structure, including a plurality of crossbar type memory arrays, is especially esteemed as a structure for a high-capacity memory device using a resistive memory device.
However, implementing a high-capacity memory device by stacking a plurality of memory arrays requires interconnections and contacts for connecting the memory array of each layer to peripheral circuits such as a driver and a sense amplifier (SA) formed on a substrate. These interconnections and contacts increase the size of a semiconductor device and degrade the operation characteristics.
Specifically, in order to form the contacts for connecting the memory array of each layer to the peripheral circuits, a separate space for the contacts should be prepared at the center or the edge of the memory array of each layer, thus increasing the size of the semiconductor device. Also, the structure of interconnections for connection of the contacts formed in a plurality of layers is complicated and the space occupied for forming the interconnections is increased, thus further increasing the size of the semiconductor device.
Also, as a design rule decreases, the critical dimension of an interconnection decreases, thus increasing the resistance of the interconnection. The increase in the resistance of the interconnection may cause a loading resistance to be connected to the resistive memory device, thus making it difficult to accurately control the resistive memory device formed in each layer.